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        <p>​        原文地址：<a target="_blank" rel="noopener" href="https://zhuanlan.zhihu.com/p/69415960">https://zhuanlan.zhihu.com/p/69415960</a></p>
<h3 id="一、FPGA设计流程"><a href="#一、FPGA设计流程" class="headerlink" title="一、FPGA设计流程"></a>一、FPGA设计流程</h3><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191320866.png" style="zoom:80%;">

<h4 id="1-设计定义"><a href="#1-设计定义" class="headerlink" title="1.设计定义"></a>1.设计定义</h4><p>​        设计定义阶段主要进行方案验证、系统设计和FPGA芯片选型等准备工作。根据任务要求，评估系统的指标和复杂度，对工作速度和芯片本身的资源、成本等方面进行权衡，选择合理的设计方案和合适的器件类型。</p>
<p>​        这个阶段往往会花费大量的时间，这个阶段之后一般已经完成了系统建模，功能划分，模块划分以及设计文档的撰写等工作。</p>
<h4 id="2-代码实现"><a href="#2-代码实现" class="headerlink" title="2.代码实现"></a>2.代码实现</h4><p>​        代码实现阶段是将划分好的各功能模块用硬件描述语言表达出来，常用的硬件描述语言有Verilog HDL和VHDL。下面是一个四选一电路的代码实现过程：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191321058.png" style="zoom:47%;">

<h4 id="3-功能仿真"><a href="#3-功能仿真" class="headerlink" title="3.功能仿真"></a>3.功能仿真</h4><p>​        功能仿真是在编译之前对用户所设计的电路进行逻辑功能验证，<strong>此时的仿真没有延迟信息，仅对初步的功能进行检测</strong>。这里我们补充一个延迟类型的知识点：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191323798.webp" style="zoom:63%;">

<p>​        我们知道信号在电路中传输时会有两种延迟：器件延迟和路径延迟。</p>
<p>​        顾名思义，器件延迟是信号在经过器件传输时的延迟时间，器件延迟与器件本身特质相关；路径延迟是信号经过连接线时的延迟时间，与连线长度成正比。</p>
<p>​        上图中信号从a到b的延迟时间为T1+T2+T3+T4+T5，其中器件延迟是T1、T3、T5，路径延迟是T2、T4。在功能仿真中，这些延迟信息都为零。</p>
<h4 id="4-逻辑综合"><a href="#4-逻辑综合" class="headerlink" title="4.逻辑综合"></a>4.逻辑综合</h4><p>​        逻辑综合的概念是：将高级抽象层次的语言描述转化成较低层次的电路结构。</p>
<p>​        也就是说将硬件描述语言描述的电路逻辑转化成与门、或门、非门、触发器等基本逻辑单元的互连关系，也就是我们常说的门级网表。。</p>
<p>​        还是以四选一电路为例，综合过程将Verilog代码翻译成了门级互连网表。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191328086.png" style="zoom:67%;">

<p>​        综合的概念很重要，利用Verilog 做电路设计时我们总是强调可综合的概念，可综合就是我们的这段代码可以被翻译成门级电路，不可综合就是代码不能被翻译成与之对应的门级电路。</p>
<p>​        综合是创造性的转化过程，它不但能翻译我们的电路，还能够优化我们的电路，比如去除电路描述中冗余的电路结构，或者复用功能相同的电路结构。</p>
<p>​        Verilog中可综合的语法多用于电路设计，那么为什么还要有不可综合的语法呢？不可综合的语法用于仿真测试。</p>
<h4 id="5-前仿真"><a href="#5-前仿真" class="headerlink" title="5.前仿真"></a>5.前仿真</h4><p>​        前仿真也叫做综合后仿真，仿真时，把综合生成的标准延时文件反标注到综合仿真模型中去。</p>
<p>​        因为综合后只能体现基本的逻辑门之间的互连关系，<strong>并不是实物电路，没有连线长度信息，所以前仿真只能评估门延时带来的影响</strong>，不能估计路径延时，前仿真结果和布线后实际情况还有一定的差距，并不十分准确。</p>
<p>​        目前的综合工具较为成熟，一般的设计可以省略这一步。但如果布局布线后发现电路功能与设计意图不符，就需要回溯到前仿真来确定问题所在。</p>
<h4 id="6-布局布线"><a href="#6-布局布线" class="headerlink" title="6.布局布线"></a>6.布局布线</h4><p>​        综合后生成的门级网表只是表示了门与门之间虚拟的连接关系，并没有规定每个门的位置以及连线长度等。布局布线就是一个将门级网表中的门的位置以及连线信息确定下来的过程。</p>
<p>​        综合后生成的门级网表只是虚拟的连接关系，并没有反应到实物上去。布局布线有时也叫作实现与布局布线，布局布线将逻辑网表中的门级连接关系配置到FPGA芯片内部的固有硬件结构上。布局布线过程将每一个门实际配置到固定位置的可编程逻辑块（CLB）中，</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191338873.png" style="zoom:67%;">

<p>​        在解释布局布线之前，我们先回顾一下FPGA的结构，我们知道FPGA可重复编程的基础是拥有巨量的可配置逻辑块（CLB）、丰富的布线资源以及其他资源</p>
<p>​        ①布局</p>
<p>​        布局的过程就是将门级网表中的每一个门“安置”到CLB中的过程，这个过程是一个映射的过程。</p>
<p>​        ②布线</p>
<p>​        布线是利用FPGA中丰富的布线资源将CLB根据逻辑关系连接在一起的过程。</p>
<p>​        逻辑门的映射位置不是随意的，是FPGA设计软件经过算法计算后精心排列的一般的布局布线策略是占用最少的CLB并且连线尽量短，也就是面积和速度最优。</p>
<p>​        布局布线策略有两种：速度优先和面积优先，往往不能同时达到两者皆最优，所以布局布线时需要在速度最优和面积最优之间做出选择。</p>
<p>​        布局布线后就可以进行静态时序分析了，<strong>静态时序分析的方法是在布局布线后的实际电路中寻找寄存器和寄存器之间的最长路径延迟，通过最大延迟可以得出系统最大时钟速率</strong>。静态时序分析也是EDA工具自动完成，延迟路径信息可以在生成的时序报告中分析。</p>
<h4 id="7-后仿真"><a href="#7-后仿真" class="headerlink" title="7.后仿真"></a>7.后仿真</h4><p>​        后仿真也称为时序仿真，是将布局布线的延时信息反标注到设计网表中来检测有无时序违规。</p>
<p>​        经过布局布线后，门与门之间的连线长度也确定了，所以后仿真包含的延迟信息最全，也最精确，能更好的反映芯片的额实际工作情况。</p>
<p>​        现在我们可以总结一下功能仿真、前仿真和后仿真的区别了：</p>
<p>​        <strong>功能仿真</strong>：无延迟信息；</p>
<p>​        <strong>前仿真</strong>：只有门级的延迟；</p>
<p>​        <strong>后仿真</strong>：门级延迟和连线延迟</p>
<h4 id="8-板级调试"><a href="#8-板级调试" class="headerlink" title="8.板级调试"></a>8.板级调试</h4><p>​        我们的FPGA设计不能只在电脑上跑仿真，最终还是要在电路板上应用起来的，设计的最后一步就是板级测试了，将EDA软件产生的数据文件（位数据流文件）下载到FPGA芯片中，进行实际的测试。</p>
<h3 id="二、FPGA设计流程直观对比"><a href="#二、FPGA设计流程直观对比" class="headerlink" title="二、FPGA设计流程直观对比"></a>二、FPGA设计流程直观对比</h3><p>​        为了方便初学者门能更快的了解FPGA的设计流程，看下面这个例子：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191354629.png" style="zoom:60%;">

<p>​        代码实现，综合和布局布线时FPGA设计流程中的几个关键步骤，下面我们打个比方加深理解一下这几个步骤是干什么的：</p>
<p>​        <strong>代码实现</strong>：比如我要盖一座房子，我把房子的特点描述出来：比如面积100平米、带阳台、欧式装修风格、挑高3米、一室两厅一厨一卫、卧室木地板客厅瓷砖。。。等等要求，这个描述房屋特点的过程就好比我们用Verilog描述电路功能的过程。</p>
<p>​        <strong>逻辑综合</strong>：建筑师根据我们的要求画出施工图纸，施工图纸将我的需求数字化、具体化，比如这个墙有多高，门有多宽，窗户面积等等，这个过程就好比综合的过程，将房屋需求翻译成具体的数字化图纸，只不过综合是将电路功能翻译成门级网表，建筑师干的活就是综合工具软件干的活。</p>
<p>​        <strong>布局布线</strong>：工人拿会根据图纸（综合后网表），用砖、水泥、钢筋、木材等材料建造施工的过程就好比布局布线的过程。图纸规定了一面墙，但是没有规定具体用哪一块砖来砌墙，工人可以自主决定用哪些砖。布局布线是根据综合后的网表（施工图纸），利用FPGA芯片内部的可编程逻辑块（CLB），布线资源，时钟资源，存储资源等搭建电路的过程。</p>
<p>​        综合和布局布线的过程中会涉及到约束策略的问题，比如管脚约束、时钟约束、面积和速度优先级等。这些概念在盖房子的过程中也有对应，比如你可以跟建筑师要求阳台大小、卧室朝向、门窗高度等，采购建筑材料时，你也会控制成本和质量之间的平衡。这些都类似于综合和布局布线过程中的约束条件。</p>

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